Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common and important semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily-doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. Punchthrough and voltage threshold implants may also be performed in the channel region 107. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
The source/drain regions 105, illustrated in FIG. 1, may include lightly-doped-drain (LDD) structures. Each LDD structure includes a lightly-doped, lower conductivity (LDD) region 106 near the channel region 107 and a heavily-doped, higher conductivity region 104 typically connected to the source/drain terminal. The LDD region 106 can be formed by lateral thermal diffusion from a more heavily doped region 104. Alternatively, LDD structures can be formed by implanting a first dopant into active regions adjacent the gate electrode 103 at relatively low concentration levels to form the lightly-doped regions 106, forming spacers 102 on sidewalls of the gate electrode 103, and implanting a second dopant into the active regions at higher concentration levels to form the heavily-doped regions 104. The substrate is typically annealed to drive the dopant in the heavily-doped regions deeper into the substrate 101.
Conducting lines (not shown) are formed to connect the gate electrode 103 and the active regions 105 to other devices. To facilitate the contact between the gate electrode 103 and the active regions 105 (particularly when these structures are made using silicon or polysilicon), a metal film is formed over the gate electrode and active regions and the metal is reacted to form a silicide with the exposed silicon. The excess metal is then removed leaving the silicide terminals. Even if spacers are not used to form LDD structures, spacers may be placed on the sidewalls of a gate electrode to prevent silicidation of those sidewalls and restrict the silicidation to the exposed top portion of the gate electrode and the exposed active regions. The spacers prevent or reduce the likelihood of an unwanted short between the gate electrode and the active regions.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET). Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices.
The fabrication of MOS devices, including NMOS, PMOS, and CMOS devices, is highly complex and associated with a number of potential problems. One significant problem is current leakage from active regions to the substrate. Another significant problem, more closely associated with CMOS devices, is known as latchup. Latchup causes the device to source large currents and typically occurs with the formation of a parasitic three-terminal semiconductor device from an active region of the device, a doped well containing the active regions, and the surrounding substrate. A variety of methods have been used to prevent latchup and to reduce current leakage. Such methods include forming isolation regions between neighboring devices and forming punchthrough regions, using the opposite type of dopant as the active regions, below the channel region near the bottom of the active regions. However, as devices become smaller and fabrication complexity increases, new technologies are needed to address these issues.
In addition, each of the steps in the formation of a semiconductor device give rise to additional potential errors in the fabrication of the device and require additional periods of time. Sources of error include, for example, misalignment of device structures, incorrect thicknesses, and shorted structures. There is a need for methods and devices that reduce the number of steps and the time in the fabrication of reliable semiconductor devices. Such methods may include, for example, the formation of two or more different parts of the device using the same process steps.